1. Field of the Invention
The present invention relates to a refresh method of a memory array and a refresh circuit.
2. Description of Related Art
Along with the development of the fabricating process, embedded memories occupies an increasing portion in a highly integrated a system on a chip (SOC). According to researches, it is forecasted that the embedded-memories will occupy 60% of the SOC. Therefore, it is an important topic to improve the efficiency of the memory and reduce the power consumption when raising an integration of the embedded memory.
FIG. 1 is a structure diagram illustrating a dynamic random access memory (DRAM) 100. Referring to FIG. 1, a basic structure of the DRAM 100 includes a memory array 110, a multiplexer 120, a row address decoder 130, a column selector 140, a binary counter 150, a sense amplifier 160, and a pre-charge circuit 170. The memory array 110 mainly includes a plurality of word lines 112 and a plurality of bit lines 114. The word lines 112 and the bit lines 114 cross each other. Each of intersections has a memory cell 116. The memory array 110 is constituted by a plurality of memory cells 116. Each of the memory cells is constituted by a transistor and a storage capacitor.
When the DRAM 100 receives an access row address (ARA), a row address decoder 130 decodes the ARA first. Then, the word line 112 corresponding to the ARA is enabled by the multiplexer 120 in order to activate all of the transistors on the word line 112. After a pre-charge voltage Vprecharge is applied to the pre-charge circuit 170, electric charges stored in the capacitor flow to the bit lines 114 in a longitudinal direction. Then, data is amplified by means of the sense amplifier 160 according to a reference voltage VREF. A column address (CA) is transmitted to a column decoder 142, and thereby the data corresponding to the CA is read or written. After performing a reading operation or a writing operation, the data returns to the memory cell 116 through a feedback circuit.
It should be noted that even the transistor in the memory cell 116 is in a close status, the electric charges stored in the capacitor are decreased as the time goes by, so that the data disappear. Therefore, it is required to provide a mechanism for refreshing the data periodically in a memory. Generally, the data is refreshed in every time interval. For example, when the electric charges are decreased to a minimum detectable electric charge, a system provides a refresh address (REFA) by using a binary counter 150, and the system controls the multiplexer 120 to select and output the REFA.
After the REFA is decoded by the row address decoder 130, the word line corresponding to the REFA is enabled to activate the transistors of all of the memory cells 116 on the corresponding word line 112, so that the electric charges in the capacitor flow to the longitudinal bit line 114. Afterwards, upon amplifying the data by the sense amplifier 160, the data of the address in the memory is refreshed before the data of the address disappear. When a refresh operation of the memory is performed, the access operation on the memory has to be stopped. Hence, the work efficiency of the memory is affected.
Presently, various methods for improving the work efficiency of the memory are provided. For example, the size of the capacitor is increased, or a current leakage problem is improved, thereby prolonging the time taken by the electric charges in the capacitor to be decreased to the minimum detectable electric charge. However, under the circumstance that the fabricating process is not changed, the work efficiency of the memory usually is increased by reducing the refresh times of the memory. As shown in FIG. 1 as an example, after the system performs the read operation or a write operation, all of the data go back to a memory unit 101. Thereby, the memory unit 101 does not need to be refreshed.
As disclosed in the U.S. Pat. No. 6,154,409, a self row-identified hidden refresh circuit for refreshing a pseudo static random access memory (SRAM) is provided. As shown in FIG. 2, the memory structure of the patent includes a controller 201, a refresh counter 202, a latchable burst array 203, a row decoder 204, a multiplexer 205, a memory array 206, and a column decoder 207. A row address (RA) is provided to the row decoder 204, and a column address (CA) is provided to the column decoder 207. According to the patent, if the memory needs to be accessed at the same time when the controller 201 is performing the refresh operation, it is determined whether the remained time is sufficient to halt the refresh operation.
If the remained time is sufficient, the latchable burst array 203 is used to record the memory row pending to be refreshed, and the access operation is performed first. After the access operation from the outside is completed, or the remained time of the refresh period is only enough to refresh the memory rows not refreshed, the controller 201 completes the refresh operation on the memory rows not refreshed. The refresh operation starts from the memory rows of which the refresh operation is halted.
In U.S. Pat. No. 6,094,705, a method and a system for selective refresh for a memory array are disclosed. As shown in FIG. 3, the structure of the memory device includes a memory array 301, a sense amplifier 302, a column decoder 303, a row decoder 304, a multiplexer 305, a memory access controller 306, and a refresh controller 307.
The patent mainly utilizes a bit register 308 to record the status of a valid bit corresponding to each of the memory rows. When the memory access controller 306 sends a refresh instruction, a binary counter 309 of the refresh controller 307 generates REFAs one by one, and the refresh controller 307 compares the valid bit with the corresponding REFA. If the memory row corresponding to the REFA is invalid or has been written, the refresh operation does not need to be performed.